EP910LI-35Y vs EP910LI-40 Comparison
Detailed side-by-side comparison of EP910LI-35Y by Intel and EP910LI-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-35Y | EP910LI-40 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Usable Gates | 450 | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | [DATA_NEEDED: maximum toggle frequency in MHz] | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Option | L (low-power CMOS) | — |
| Temperature Grade | Industrial (-40 °C to +85 °C) | — |
| Package | PLCC-44 (J-lead) | PLCC-44 (J-lead, windowed ceramic) |
| Mounting Type | Surface Mount | Surface Mount (socket-compatible) |
| Lead Finish | Lead-free (Y suffix, RoHS-compliant) | — |
| I/O Pins | 24 | 24 bidirectional |
| Dedicated Inputs | 36 | 12 |
| Technology | CMOS EPROM/UV-erasable | Low-power CMOS (L-suffix) |
| RoHS Status | Compliant (Y suffix) | Non-compliant (windowed ceramic PLCC, legacy) |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Maximum Logic Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| Operating Temperature | — | -40C to +85C (industrial, I-suffix) |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |