EP910LI-50 vs EP910LI-35 Comparison
Detailed side-by-side comparison of EP910LI-50 by Altera and EP910LI-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-50 | EP910LI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 900 |
| Propagation Delay (tPD) | 50 ns | — |
| Package Type | CERDIP-40 (L) | — |
| Package Pin Count | 40 | — |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| Operating Temperature | -40C to +85C (industrial) | -40 °C to +85 °C (Industrial) |
| Technology | CMOS, UV-erasable EPROM | — |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Programming Method | EPROM programmer (UV-erasable window) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Device Series | — | EP910 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Supply Voltage | — | 5 V (4.75 V to 5.25 V) |
| Package | — | 44-pin PLCC (J-lead) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Mounting Type | — | Surface Mount |
| Lead Pitch | — | 1.27 mm |