EP910LI-50 vs EP910LI-35 对比
详细并排对比 EP910LI-50 出自 Altera 和 EP910LI-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910LI-50 | EP910LI-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $65.00 | $25.80 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 900 |
| Propagation Delay (tPD) | 50 ns | — |
| Package Type | CERDIP-40 (L) | — |
| Package Pin Count | 40 | — |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| 工作温度 | -40C to +85C (industrial) | -40 °C to +85 °C (Industrial) |
| Technology | CMOS, UV-erasable EPROM | — |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Programming Method | EPROM programmer (UV-erasable window) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Device Series | — | EP910 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| 电源电压 | — | 5 V (4.75 V to 5.25 V) |
| 封装 | — | 44-pin PLCC (J-lead) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| 安装类型 | — | Surface Mount |
| Lead Pitch | — | 1.27 mm |