EP910PC-0 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910PC-0 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-0 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.70 | $15.60 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Usable Gates | 900 gates | β |
| Macrocells | 24 | 24 |
| Logic Blocks | 6 (4 macrocells each) | β |
| Dedicated Inputs | 10 | 36 |
| I/O Pins | 24 | β |
| Package | PDIP-40 (Plastic DIP, 40-pin) | DIP-40 (through-hole, 600 mil) |
| Speed Grade | -0 (slowest) | β |
| Supply Voltage | 5 V (single supply) | 5 V |
| Process Technology | CMOS | CMOS |
| Logic Compatibility | 100% TTL emulation | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable / OTP | UV-Erasable / OTP |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Architecture | β | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | β | 900 usable gates |
| Propagation Delay (tPD) | β | 30 ns (max) |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |