EP910PC-0 vs EP910DC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-0 sa pamamagitan ng Altera at EP910DC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-0 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Logic Blocks | 6 (4 macrocells each) | — |
| Dedicated Inputs | 10 | 36 |
| I/O Pins | 24 | — |
| Packhaging | PDIP-40 (Plastic DIP, 40-pin) | DIP-40 (through-hole, 600 mil) |
| Speed Grade | -0 (slowest) | — |
| Volte ng Pagbibigay | 5 V (single supply) | 5 V |
| Process Technology | CMOS | CMOS |
| Logic Compatibility | 100% TTL emulation | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable / OTP | UV-Erasable / OTP |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |