EP910PC-15T vs EP910PC-25 Comparison
Detailed side-by-side comparison of EP910PC-15T by Altera and EP910PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-15T | EP910PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.20 | $16.92 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EPLD | β |
| Macrocell Count | 24 | β |
| Dedicated Input Pins | 10 | β |
| Pin-to-Pin Delay (tPD) | 15 ns | 25 ns |
| Speed Grade | -15 (15 ns) | β |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V +/- 10% |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM |
| Package | 40-pin PDIP (Plastic DIP) | PDIP-24 (Plastic DIP) |
| Mounting Type | Through-hole (DIP) | β |
| Output Drive Current | [DATA_NEEDED: IOL per output] | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | β |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Security Bit | Yes (design protection) | β |
| Tape and Reel | Yes (suffix T) | β |
| Product Family | β | Classic EPLD |
| Usable Gates | β | 900 |
| Integration Gates (typical) | β | 4800 |
| Macrocells | β | 24 |
| Maximum Operating Frequency (fMAX) | β | 33.3 MHz |
| Pin Count | β | 24 |
| Dedicated Inputs | β | 10 |
| Dedicated I/O Pins | β | 12 |
| TTL Compatibility | β | 100% TTL emulation |
| Erasure Method | β | Not erasable in plastic package (windowless) |