EP910PC-15T vs EP910PC-25 Vergleich
Detaillierter Direktvergleich von EP910PC-15T von Altera und EP910PC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-15T | EP910PC-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,20 | $16,92 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | 25 ns |
| Speed Grade | -15 (15 ns) | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V +/- 10% |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM |
| Gehäuse | 40-pin PDIP (Plastic DIP) | PDIP-24 (Plastic DIP) |
| Montageart | Through-hole (DIP) | — |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Product Family | — | Classic EPLD |
| Usable Gates | — | 900 |
| Integration Gates (typical) | — | 4800 |
| Macrocells | — | 24 |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Pin-Anzahl | — | 24 |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |