EP910PC-15T vs EP910PC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-15T sa pamamagitan ng Altera at EP910PC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-15T | EP910PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | 25 ns |
| Speed Grade | -15 (15 ns) | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V +/- 10% |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM |
| Packhaging | 40-pin PDIP (Plastic DIP) | PDIP-24 (Plastic DIP) |
| Uri ng Pagpapasok | Through-hole (DIP) | — |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Product Family | — | Classic EPLD |
| Usable Gates | — | 900 |
| Integration Gates (typical) | — | 4800 |
| Macrocells | — | 24 |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Bilang ng Pin | — | 24 |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |