EP910PC-25 vs EP910PC-15T Comparison
Detailed side-by-side comparison of EP910PC-25 by Altera and EP910PC-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-25 | EP910PC-15T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.92 | $14.20 |
| Product Family | Classic EPLD | β |
| Usable Gates | 900 | β |
| Integration Gates (typical) | 4800 | β |
| Macrocells | 24 | β |
| Pin-to-Pin Delay (tPD) | 25 ns | 15 ns |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V (nominal) |
| Technology | CMOS EPROM | CMOS, UV-erasable / OTP |
| Package | PDIP-24 (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Pin Count | 24 | β |
| Dedicated Inputs | 10 | β |
| Dedicated I/O Pins | 12 | β |
| TTL Compatibility | 100% TTL emulation | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Family | β | Altera Classic EPLD |
| Macrocell Count | β | 24 |
| Dedicated Input Pins | β | 10 |
| Speed Grade | β | -15 (15 ns) |
| Mounting Type | β | Through-hole (DIP) |
| Output Drive Current | β | [DATA_NEEDED: IOL per output] |
| Logic Capacity | β | 24 macrocells / 72 product terms (typical Classic architecture) |
| Programming Method | β | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Security Bit | β | Yes (design protection) |
| Tape and Reel | β | Yes (suffix T) |