EP910PC-25 vs EP910PC-15T Comparaison
Comparaison détaillée côte à côte de EP910PC-25 par Altera et EP910PC-15T par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PC-25 | EP910PC-15T |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $16,92 | $14,20 |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | — |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | — |
| Pin-to-Pin Delay (tPD) | 25 ns | 15 ns |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V (nominal) |
| Technology | CMOS EPROM | CMOS, UV-erasable / OTP |
| Boîtier | PDIP-24 (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Nombre de broches | 24 | — |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Température de fonctionnement | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Macrocell Count | — | 24 |
| Dedicated Input Pins | — | 10 |
| Speed Grade | — | -15 (15 ns) |
| Type de montage | — | Through-hole (DIP) |
| Output Drive Current | — | [DATA_NEEDED: IOL per output] |
| Logic Capacity | — | 24 macrocells / 72 product terms (typical Classic architecture) |
| Programming Method | — | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| Statut RoHS | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Security Bit | — | Yes (design protection) |
| Tape and Reel | — | Yes (suffix T) |