EP910PC-25 vs EP910PC-35 Comparison
Detailed side-by-side comparison of EP910PC-25 by Altera and EP910PC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-25 | EP910PC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.92 | $8.70 |
| Product Family | Classic EPLD | β |
| Usable Gates | 900 | β |
| Integration Gates (typical) | 4800 | β |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | β |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V +/- 10% | β |
| Technology | CMOS EPROM | CMOS, UV-erasable/OTP |
| Package | PDIP-24 (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Pin Count | 24 | β |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | β |
| TTL Compatibility | 100% TTL emulation | β |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Erasure Method | Not erasable in plastic package (windowless) | β |
| Family | β | Classic EPLD |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| I/O Pins | β | 24 |
| Total Inputs | β | 36 |
| Product Terms | β | 240 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Counter Frequency | β | 37 MHz |
| Internal Performance Frequency | β | 100 MHz |
| Supply Voltage | β | 5 V |
| Mounting Type | β | Through-Hole |
| Architecture | β | PAL-type sum-of-products, AND/OR array |
| Programming Method | β | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Compliance / RoHS | β | [DATA_NEEDED: RoHS status - legacy part] |