EP910PC-25 vs EP910PC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-25 sa pamamagitan ng Altera at EP910PC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-25 | EP910PC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | — |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| Technology | CMOS EPROM | CMOS, UV-erasable/OTP |
| Packhaging | PDIP-24 (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Bilang ng Pin | 24 | — |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Volte ng Pagbibigay | — | 5 V |
| Uri ng Pagpapasok | — | Through-Hole |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Programming Method | — | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |