EP910PC-25 vs EP910PC-35 Vergleich
Detaillierter Direktvergleich von EP910PC-25 von Altera und EP910PC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-25 | EP910PC-35 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,92 | $8,70 |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | — |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| Technology | CMOS EPROM | CMOS, UV-erasable/OTP |
| Gehäuse | PDIP-24 (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Pin-Anzahl | 24 | — |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Versorgungsspannung | — | 5 V |
| Montageart | — | Through-Hole |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Programming Method | — | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |