EP910PC-30 vs EP910PC-35 Comparison
Detailed side-by-side comparison of EP910PC-30 by Altera and EP910PC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-30 | EP910PC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.50 | $8.70 |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | β |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | β |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V Β±10% | β |
| Logic Inputs | 36 dedicated | β |
| I/O Pins | 12 bidirectional | 24 |
| Logic Array Blocks (LABs) | 4 | β |
| Package | PDIP-40 (plastic DIP, 0.6 inch) | 40-pin PDIP (Plastic DIP) |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM cell | β |
| TTL Emulation | 100% TTL-compatible | β |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | β |
| RoHS Status | Non-compliant (contains lead, PDIP package) | β |
| Mounting Type | Through-hole DIP | Through-Hole |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | β | 12 |
| Total Inputs | β | 36 |
| Product Terms | β | 240 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Counter Frequency | β | 37 MHz |
| Internal Performance Frequency | β | 100 MHz |
| Technology | β | CMOS, UV-erasable/OTP |
| Supply Voltage | β | 5 V |
| Architecture | β | PAL-type sum-of-products, AND/OR array |
| Programming Method | β | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Compliance / RoHS | β | [DATA_NEEDED: RoHS status - legacy part] |