EP910PC-30 vs EP910PC-35 Comparaison
Comparaison détaillée côte à côte de EP910PC-30 par Altera et EP910PC-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PC-30 | EP910PC-35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $6,50 | $8,70 |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | — |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | — |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | 24 |
| Logic Array Blocks (LABs) | 4 | — |
| Boîtier | PDIP-40 (plastic DIP, 0.6 inch) | 40-pin PDIP (Plastic DIP) |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM cell | — |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| Statut RoHS | Non-compliant (contains lead, PDIP package) | — |
| Type de montage | Through-hole DIP | Through-Hole |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | — | 12 |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Technology | — | CMOS, UV-erasable/OTP |
| Tension d'alimentation | — | 5 V |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Programming Method | — | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |