EP910PC-30 vs EP910PC-35 比較
詳細な並列比較: EP910PC-30 メーカー: Altera および EP910PC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PC-30 | EP910PC-35 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $6.50 | $8.70 |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | — |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | — |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | 24 |
| Logic Array Blocks (LABs) | 4 | — |
| パッケージ | PDIP-40 (plastic DIP, 0.6 inch) | 40-pin PDIP (Plastic DIP) |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM cell | — |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| RoHS ステータス | Non-compliant (contains lead, PDIP package) | — |
| 実装タイプ | Through-hole DIP | Through-Hole |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | — | 12 |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Technology | — | CMOS, UV-erasable/OTP |
| 電源電圧 | — | 5 V |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Programming Method | — | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |