EP910PC30T vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910PC30T by Altera and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC30T | EP910PC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $6.50 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Series | EP910 | β |
| Number of Macrocells | 24 | β |
| Number of I/O Pins | 24 | β |
| Number of Dedicated Inputs | 12 | β |
| Maximum Product Terms | 240 | β |
| Propagation Delay (tPD) | 30 ns | β |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V Β±10% |
| Process Technology | CMOS | β |
| Programmable Logic Architecture | PAL-type sum-of-products, EPLD | β |
| Package | 24-pin PDIP (PC) | PDIP-40 (plastic DIP, 0.6 inch) |
| Mounting Type | Through-Hole (THT) | Through-hole DIP |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Speed Grade | -30 (30 ns tPD) | β |
| Programming Technology | EPROM (OTP in plastic package, UV-erasable in windowed package) | UV-erasable EPROM cell |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains lead, PDIP package) |
| Pin Count | 24 | β |
| Macrocells | β | 24 |
| Usable Gates | β | ~450 |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Logic Inputs | β | 36 dedicated |
| I/O Pins | β | 12 bidirectional |
| Logic Array Blocks (LABs) | β | 4 |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |