EP910PC30T vs EP910PC-30 比較
詳細並排比較 EP910PC30T 由 Altera 與 EP910PC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC30T | EP910PC-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Series | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of I/O Pins | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Maximum Product Terms | 240 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V ±10% |
| Process Technology | CMOS | — |
| Programmable Logic Architecture | PAL-type sum-of-products, EPLD | — |
| 封裝 | 24-pin PDIP (PC) | PDIP-40 (plastic DIP, 0.6 inch) |
| 安裝類型 | Through-Hole (THT) | Through-hole DIP |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Speed Grade | -30 (30 ns tPD) | — |
| Programming Technology | EPROM (OTP in plastic package, UV-erasable in windowed package) | UV-erasable EPROM cell |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains lead, PDIP package) |
| 腳位數 | 24 | — |
| Macrocells | — | 24 |
| Usable Gates | — | ~450 |
| Pin-to-Pin Propagation Delay (tPD) | — | 30 ns |
| Maximum Counter Frequency (fCNT) | — | 33.3 MHz |
| Logic Inputs | — | 36 dedicated |
| I/O Pins | — | 12 bidirectional |
| Logic Array Blocks (LABs) | — | 4 |
| TTL Emulation | — | 100% TTL-compatible |
| Power Dissipation | — | [DATA_NEEDED: power dissipation mW] |