EP910PI-15T vs EP910PI-20T Comparison
Detailed side-by-side comparison of EP910PI-15T by Altera and EP910PI-20T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-15T | EP910PI-20T |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Supply Voltage | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | CMOS EPROM (UV-erasable) |
| Package | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (PI) |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Operating Temperature | [DATA_NEEDED: industrial/commercial temp range] | [DATA_NEEDED: operating temperature range] |
| Programming | JEDEC-standard, serial/parallel programmer | Standard EPROM programmer, JEDEC map |
| RoHS Status | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | unknown |
| Device | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tpd) | — | 20 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Pins | — | 20 |
| Number of Pins | — | 40 |
| Lifecycle Status | — | Not Recommended for New Designs (NRND) |