EP910PI-30T vs EP910PI-35T Comparison
Detailed side-by-side comparison of EP910PI-30T by Altera and EP910PI-35T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-30T | EP910PI-35T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | 450 |
| Dedicated Inputs | 10 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| Mounting Type | Through-Hole | Through-Hole |
| Operating Temperature | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature range] |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Pin-to-Pin Logic Delay (tpd) | — | 35 ns |
| Counter Frequency (fCNT) | — | 28.6 MHz |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Process Technology | — | CMOS |
| Package | — | 40-pin PDIP (Plastic DIP) |
| Programming Method | — | UV-erasable, EPROM technology |
| On-board Test Circuitry | — | Yes (logic test mode for AC verification) |
| MSL Level | — | [DATA_NEEDED: MSL level] |