EP910PI-30T vs EP910PI-35T Comparación
Comparación detallada lado a lado de EP910PI-30T por Altera y EP910PI-35T por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-30T | EP910PI-35T |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $11,15 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | 450 |
| Dedicated Inputs | 10 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| Tipo de montaje | Through-Hole | Through-Hole |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature range] |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Pin-to-Pin Logic Delay (tpd) | — | 35 ns |
| Counter Frequency (fCNT) | — | 28.6 MHz |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Process Technology | — | CMOS |
| Encapsulado | — | 40-pin PDIP (Plastic DIP) |
| Programming Method | — | UV-erasable, EPROM technology |
| On-board Test Circuitry | — | Yes (logic test mode for AC verification) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |