EP910PI-30T vs EP910PI-35T 比較
詳細並排比較 EP910PI-30T 由 Altera 與 EP910PI-35T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-30T | EP910PI-35T |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | 450 |
| Dedicated Inputs | 10 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| 安裝類型 | Through-Hole | Through-Hole |
| 工作溫度 | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature range] |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Pin-to-Pin Logic Delay (tpd) | — | 35 ns |
| Counter Frequency (fCNT) | — | 28.6 MHz |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Process Technology | — | CMOS |
| 封裝 | — | 40-pin PDIP (Plastic DIP) |
| Programming Method | — | UV-erasable, EPROM technology |
| On-board Test Circuitry | — | Yes (logic test mode for AC verification) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |