EPC1441TI32N vs EPC144TC32N Comparison

Detailed side-by-side comparison of EPC1441TI32N by Intel and EPC144TC32N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPC1441TI32N

EPC1441TI32N - 440Kb FPGA Config PROM, 32-TQFP | Intel / Altera

EPC1441TI32N βœ“ Active

Specification Comparison

Parameter EPC1441TI32N EPC144TC32N
Brand Intel Altera
Category Memory ICs FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.45 $3.85
Memory Type OTP Configuration PROM (serial) β€”
Memory Density 440 kbit (440,800 bits) β€”
Number of Words 440,800 words β€”
Bits per Word 1 bit β€”
Memory Technology EPROM (one-time programmable) β€”
Supply Voltage 3.3 V β€”
Interface Type Altera passive-serial (FPGA configuration) β€”
Programming Interface IEEE 1149.1 (JTAG) - 5 V and 3.3 V ISP IEEE Std 1149.1 JTAG (TMS, TCK, TDI, TDO)
Max Serial Clock 10 MHz (per datasheet.com) / 8 MHz (per Mouser listing) β€”
Package Type TQFP-32 (plastic, 7x7 mm) β€”
Mounting Type Surface Mount Surface Mount
Operating Temperature Grade Industrial β€”
Number of Pins 32 β€”
RoHS Status Compliant β€”
Lead-Free Yes β€”
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX β€”
Device Type β€” Enhanced Configuration (EPC) Device, serial EEPROM
Configuration Memory Size β€” 440800 bits (approximately 54 KB)
Compatible FPGA Families β€” FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury
Configuration Interface β€” Altera serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE)
In-System Programmability β€” Yes (ISP via JTAG)
Supply Voltage VCC β€” 3.0 V to 3.6 V (typical 3.3 V)
Supply Voltage VPP β€” Generated internally (no external VPP required)
Operating Temperature β€” -40C to +85C (industrial)
Package β€” TQFP-32
Lead-Free / RoHS β€” [DATA_NEEDED: lead-free status]
MSL Level β€” [DATA_NEEDED: MSL level]
JTAG Chain Compatibility β€” Yes (shares TDI/TDO with target FPGA)
Programming Cycles β€” [DATA_NEEDED: endurance]

Datasheets & Resources

Browse All Products Create BOM Request Quote