EPC144L120 vs EPC1441LI20 Comparison

Detailed side-by-side comparison of EPC144L120 by Intel and EPC1441LI20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC144L120 EPC1441LI20
Brand Intel Intel
Category FPGA & CPLD Memory ICs
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $17.40 $8.10
Manufacturer Intel (formerly Altera) β€”
Device Family EPC1441 Configuration Device β€”
Device Function Serial Configuration Memory for Altera FPGAs β€”
Compatible FPGAs ACEX 1K, APEX 20K, FLEX 10K, Mercury β€”
Package Code L120 = 120-pin QFP β€”
Package Type QFP-120 (Plastic Quad Flat Pack) β€”
Configuration Interface Single-wire serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS)
Memory Type OTP (One-Time Programmable) CMOS OTP Configuration PROM (PROM)
Configuration Storage [DATA_NEEDED: configuration bit density in bits] β€”
Supply Voltage [DATA_NEEDED: VCC nominal range] 3.3 V
I/O Voltage Compatibility 3.3 V and 5 V (per Altera datasheet family) β€”
Programming Method Altera programming hardware via JTAG-like interface One-Time-Programmable via Altera programming hardware
Operating Temperature [DATA_NEEDED: industrial / commercial grade] -40 C to +85 C (industrial)
Mounting Type Surface Mount (QFP) β€”
MSL Level [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
RoHS Status [DATA_NEEDED: RoHS compliant status] [DATA_NEEDED: RoHS compliance status]
Lifecycle Status Not Recommended for New Designs (NRND) per Intel product page β€”
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free status] β€”
Density β€” 441 kbits (440,800 bits)
Number of Words β€” 440,800
Bits per Word β€” 1 bit
Supported FPGA Families β€” ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury
Package β€” 20-pin PLCC (J-lead, 9x9 mm)
Pin Pitch β€” 1.27 mm
Lead-Free β€” [DATA_NEEDED: lead-free status]
Configuration Time β€” Depends on FPGA bitstream length and DCLK frequency

Datasheets & Resources

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