EPC144L120 vs EPC1441LI20 比較
詳細な並列比較: EPC144L120 メーカー: Intel および EPC1441LI20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC144L120 | EPC1441LI20 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | Memory ICs |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $17.40 | $8.10 |
| Manufacturer | Intel (formerly Altera) | — |
| Device Family | EPC1441 Configuration Device | — |
| Device Function | Serial Configuration Memory for Altera FPGAs | — |
| Compatible FPGAs | ACEX 1K, APEX 20K, FLEX 10K, Mercury | — |
| Package Code | L120 = 120-pin QFP | — |
| Package Type | QFP-120 (Plastic Quad Flat Pack) | — |
| Configuration Interface | Single-wire serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| メモリタイプ | OTP (One-Time Programmable) CMOS | OTP Configuration PROM (PROM) |
| Configuration Storage | [DATA_NEEDED: configuration bit density in bits] | — |
| 電源電圧 | [DATA_NEEDED: VCC nominal range] | 3.3 V |
| I/O Voltage Compatibility | 3.3 V and 5 V (per Altera datasheet family) | — |
| Programming Method | Altera programming hardware via JTAG-like interface | One-Time-Programmable via Altera programming hardware |
| 動作温度 | [DATA_NEEDED: industrial / commercial grade] | -40 C to +85 C (industrial) |
| 実装タイプ | Surface Mount (QFP) | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| RoHS ステータス | [DATA_NEEDED: RoHS compliant status] | [DATA_NEEDED: RoHS compliance status] |
| ライフサイクル状態 | Not Recommended for New Designs (NRND) per Intel product page | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Supported FPGA Families | — | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| パッケージ | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Pin Pitch | — | 1.27 mm |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |