EPC16UI8B vs EPC16SI16N Comparison
Detailed side-by-side comparison of EPC16UI8B by Altera and EPC16SI16N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Last Time BuySpecification Comparison
| Parameter | EPC16UI8B | EPC16SI16N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Last Time Buy |
| Memory Density | 16 Mbit (2 MB) | — |
| Function | Enhanced Configuration Device for SRAM-based LUT FPGAs | — |
| Interface | Active Serial (AS), JTAG | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) |
| Supply Voltage | 2.5 V / 3.3 V | — |
| Package | USON-8 / WSON-8 (8-pin) | 16-pin SOIC (300 mil, 'SI' suffix) |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C (industrial, 'SI' suffix) |
| Architecture | Multi-page flash, up to 8 pages | — |
| In-System Programming | Yes (JTAG) | — |
| Compression Support | Yes (bitstream decompression) | — |
| Remote System Upgrade | Yes | — |
| Cascade Support | Yes (multi-FPGA) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Silicon Revision | B (second revision) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Memory Type | — | Non-volatile flash (enhanced configuration device) |
| Memory Size | — | 16 Mb (16,777,216 bits) |
| Programming Interface | — | JTAG (IEEE 1149.1 boundary scan) |
| Maximum Operating Frequency | — | 40 MHz (fast configuration mode) |
| Operating Supply Voltage | — | 3.3 V (typ) |
| Lead-Free / Finish | — | Lead-free (matte tin), 'N' suffix |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| In-System Programmability | — | Yes (via JTAG, multiple reprogramming cycles) |
| Compatible FPGA Series | — | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III |
| Configuration Daisy-Chaining | — | Supported (multiple devices / multiple FPGAs) |
| On-Chip Charge Pump | — | Integrated (no external VPP required) |