EPC1L20 vs EPC1LC20-WCEC52 Comparison

Detailed side-by-side comparison of EPC1L20 by Altera and EPC1LC20-WCEC52 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC1L20 EPC1LC20-WCEC52
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $3.75 $7.45
Memory Type OTP Configuration PROM (Flash) OTP Configuration PROM (Anti-fuse)
Memory Size 1 Mbit 1 Mbit (1,048,576 bits)
Configuration Clock (max) 8 MHz β€”
Flash Access Time 90 ns (approx.) β€”
Max Read Bandwidth 160 Mbps (16-bit DQ bus) β€”
Interface Serial / FPP configuration + JTAG (IEEE 1149.1) Serial (Altera FPP/PS configuration protocol)
Supply Voltage 3.3 V (typical) β€”
Programmability One-Time Programmable (OTP) One-Time Programmable (OTP)
Package 20-pin PLCC (9x9 mm) 20-pin PLCC (J-lead, through-hole, 9x9 mm)
Mounting Type Through-Hole / Socket β€”
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
JTAG / ISP Support Yes (IEEE 1149.1) β€”
Compatible FPGA Series Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free status]
Organization β€” 212,942 x 1 bit
Configuration Clock (DCLK) β€” 8 MHz maximum
Supply Voltage (VCC) β€” 3.3 V
I/O Voltage Tolerance β€” 5.0 V (FPGA interface)
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
Package Mounting β€” Through-hole (also accepts PLCC socket)
Compatible FPGA Families β€” Cyclone, Stratix, APEX, ACEX, MAX series
Programming Interface β€” JTAG (IEEE Std 1149.1) ISP
Pin Count β€” 20
Lifecycle Status β€” Obsolete (recommended replacement: EPCQ family or newer serial config devices)

Datasheets & Resources

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