EPC1LC20N vs EPC1LI20 Comparison
Detailed side-by-side comparison of EPC1LC20N by Intel and EPC1LI20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC1LC20N
EPC1LC20N - 1Mb OTP FPGA Configuration PROM | Intel / Altera | PLCC-20
EPC1LC20N NrndSpecification Comparison
| Parameter | EPC1LC20N | EPC1LI20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $8.50 |
| Memory Type | OTP Configuration PROM (EPROM-based) | OTP Configuration PROM (EPROM-based) |
| Memory Size | 1 Mbit | 1 Mb (1,048,576 bits) |
| Programmable Type | OTP (One-Time Programmable) | β |
| Configuration Clock Frequency | 16.7 MHz | β |
| Supply Voltage - VCCINT | 4.75 V to 5.25 V | β |
| Supply Voltage - VCCIO | 3.0 V to 3.6 V | β |
| Operating Temperature | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Package / Case | 20-LCC (J-Lead), PLCC-20 | β |
| Package Dimensions | 9 mm x 9 mm | β |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| Packaging | Tube | β |
| Configuration Interface | Serial (DATA, DCLK, nCONFIG, nSTATUS) | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Supported FPGA Families | Altera FLEX, APEX, ACEX, Mercury | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Maximum Configuration Clock | β | 8 MHz |
| Supply Voltage (VCC) | β | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | β | 12.75 V (typical, factory-programmed via JTAG) |
| Package | β | 20-pin PLCC (J-lead, 9x9 mm) |
| Pin Count | β | 20 |
| Cascading Support | β | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | β | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | β | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | β | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| MSL Level | β | 1 (per Partstack datasheet record) |