EPC1LC20N vs EPC1LI20 Comparaison
Comparaison détaillée côte à côte de EPC1LC20N par Intel et EPC1LI20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LC20N | EPC1LI20 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,40 | $8,50 |
| Type de mémoire | OTP Configuration PROM (EPROM-based) | OTP Configuration PROM (EPROM-based) |
| Taille de mémoire | 1 Mbit | 1 Mb (1,048,576 bits) |
| Programmable Type | OTP (One-Time Programmable) | — |
| Configuration Clock Frequency | 16.7 MHz | — |
| Supply Voltage - VCCINT | 4.75 V to 5.25 V | — |
| Supply Voltage - VCCIO | 3.0 V to 3.6 V | — |
| Température de fonctionnement | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Boîtier / Format | 20-LCC (J-Lead), PLCC-20 | — |
| Package Dimensions | 9 mm x 9 mm | — |
| Type de montage | Surface Mount | Surface Mount (PLCC socket compatible) |
| Packaging | Tube | — |
| Configuration Interface | Serial (DATA, DCLK, nCONFIG, nSTATUS) | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Supported FPGA Families | Altera FLEX, APEX, ACEX, Mercury | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum Configuration Clock | — | 8 MHz |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Boîtier | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Nombre de broches | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Niveau MSL | — | 1 (per Partstack datasheet record) |