EPC1LC20N vs EPC1LI20 Comparación
Comparación detallada lado a lado de EPC1LC20N por Intel y EPC1LI20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC1LC20N | EPC1LI20 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,40 | $8,50 |
| Tipo de memoria | OTP Configuration PROM (EPROM-based) | OTP Configuration PROM (EPROM-based) |
| Tamaño de memoria | 1 Mbit | 1 Mb (1,048,576 bits) |
| Programmable Type | OTP (One-Time Programmable) | — |
| Configuration Clock Frequency | 16.7 MHz | — |
| Supply Voltage - VCCINT | 4.75 V to 5.25 V | — |
| Supply Voltage - VCCIO | 3.0 V to 3.6 V | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Encapsulado / Carcasa | 20-LCC (J-Lead), PLCC-20 | — |
| Package Dimensions | 9 mm x 9 mm | — |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket compatible) |
| Packaging | Tube | — |
| Configuration Interface | Serial (DATA, DCLK, nCONFIG, nSTATUS) | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Supported FPGA Families | Altera FLEX, APEX, ACEX, Mercury | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum Configuration Clock | — | 8 MHz |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Encapsulado | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Recuento de pines | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Nivel MSL | — | 1 (per Partstack datasheet record) |