EPC22LC20 vs EPC2L120N Comparison
Detailed side-by-side comparison of EPC22LC20 by Intel and EPC2L120N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC22LC20 | EPC2L120N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.10 | $7.85 |
| Function | In-System Programmable Configuration PROM for SRAM-based FPGAs | β |
| Memory Size | 1.6 Mbit | β |
| Programmable Type | In System Programmable (IEEE 1532 / Jam STAPL) | β |
| Supply Voltage - Low Range | 3.0 V to 3.6 V | β |
| Supply Voltage - High Range | 4.75 V to 5.25 V | β |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |
| Configuration Interface | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) | β |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | β |
| Package / Case | 20-LCC (J-Lead, 9 x 9 mm) | β |
| Mounting Type | Surface Mount (PLCC socket compatible) | β |
| Packaging | Tube | β |
| Operating Temperature | 0 C to +70 C (commercial) | [DATA_NEEDED: industrial temp range] |
| Minimum DC Input Voltage | -0.3 V | β |
| Input Overshoot Tolerance | 7.0 V for <100 mA, <20 ns no-load | β |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns no-load | β |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status not in verified data] | β |
| Device Type | β | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | β | Intel (formerly Altera) |
| Family | β | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | β | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | β | 2.7 V to 3.6 V |
| 5V Tolerance | β | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | β | Up to 66 MHz |
| Configuration Clock (PS) | β | Up to 33 MHz |
| Internal Oscillator | β | 8 MHz with programmable divider |
| JTAG Interface | β | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | β | 100,000 erase/program cycles |
| Sector Erase Time | β | [DATA_NEEDED: typical sector erase time] |
| Package | β | 84-pin PLCC (J-Lead) |
| Configuration Schemes | β | FPP, PS, JTAG, daisy chain |
| RoHS Status | β | unknown |