EPC22LC20 vs EPC2L120N 比較

詳細並排比較 EPC22LC20 由 Intel 與 EPC2L120N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC22LC20 EPC2L120N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
功能 In-System Programmable Configuration PROM for SRAM-based FPGAs —
記憶體容量 1.6 Mbit —
Programmable Type In System Programmable (IEEE 1532 / Jam STAPL) —
Supply Voltage - Low Range 3.0 V to 3.6 V —
Supply Voltage - High Range 4.75 V to 5.25 V —
Supported FPGA Families ACEX 1K, APEX II, APEX 20K, FLEX 10K Cyclone, APEX, FLEX, Mercury, ACEX, Stratix
Configuration Interface Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) —
Programming Interface JTAG (IEEE 1149.1 / IEEE 1532) —
封裝 / 外殼 20-LCC (J-Lead, 9 x 9 mm) —
安裝類型 Surface Mount (PLCC socket compatible) —
Packaging Tube —
工作溫度 0 C to +70 C (commercial) [DATA_NEEDED: industrial temp range]
Minimum DC Input Voltage -0.3 V —
Input Overshoot Tolerance 7.0 V for <100 mA, <20 ns no-load —
Input Undershoot Tolerance -2.0 V for <100 mA, <20 ns no-load —
Lead-Free / RoHS [DATA_NEEDED: lead-free status not in verified data] —
Device Type — Configuration Device for SRAM-based LUT FPGAs
Manufacturer — Intel (formerly Altera)
Family — EPC2 (Enhanced Configuration Device)
Memory Capacity — 165,888 bits (400,000 gates equivalent)
Operating Voltage (VCCIO) — 2.7 V to 3.6 V
5V Tolerance — Yes (5V-tolerant I/O)
Configuration Clock (FPP) — Up to 66 MHz
Configuration Clock (PS) — Up to 33 MHz
Internal Oscillator — 8 MHz with programmable divider
JTAG Interface — IEEE Std 1149.1 compliant, ISP support
Programming Cycles — 100,000 erase/program cycles
Sector Erase Time — [DATA_NEEDED: typical sector erase time]
封裝 — 84-pin PLCC (J-Lead)
Configuration Schemes — FPP, PS, JTAG, daisy chain
RoHS 狀態 — unknown

資料表與資源

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