EPC22LC20 vs EPC2L120N Сравнение
Подробное сравнение бок о бок EPC22LC20 от Intel и EPC2L120N от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC22LC20 | EPC2L120N |
|---|---|---|
| Бренд | Intel | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $4,10 | $7,85 |
| Функция | In-System Programmable Configuration PROM for SRAM-based FPGAs | — |
| Размер памяти | 1.6 Mbit | — |
| Programmable Type | In System Programmable (IEEE 1532 / Jam STAPL) | — |
| Supply Voltage - Low Range | 3.0 V to 3.6 V | — |
| Supply Voltage - High Range | 4.75 V to 5.25 V | — |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |
| Configuration Interface | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | — |
| Корпус / Типоразмер | 20-LCC (J-Lead, 9 x 9 mm) | — |
| Тип монтажа | Surface Mount (PLCC socket compatible) | — |
| Packaging | Tube | — |
| Рабочая температура | 0 C to +70 C (commercial) | [DATA_NEEDED: industrial temp range] |
| Minimum DC Input Voltage | -0.3 V | — |
| Input Overshoot Tolerance | 7.0 V for <100 mA, <20 ns no-load | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns no-load | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status not in verified data] | — |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Корпус | — | 84-pin PLCC (J-Lead) |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Статус RoHS | — | unknown |