EPC2C20 vs EPC2-TI32N Comparison

Detailed side-by-side comparison of EPC2C20 by Altera and EPC2-TI32N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPC2C20 EPC2C20 - Altera FPGA Configuration Device

EPC2C20 - Altera FPGA Configuration Device

EPC2C20 ✓ Active

Specification Comparison

Parameter EPC2C20 EPC2-TI32N
Brand Altera Intel
Category FPGA & CPLD Memory ICs
Lifecycle Status Active NRND
Manufacturer Altera —
MPN EPC2C20 —
Device Type Configuration device integrated circuit —
Primary Function Configuration of SRAM-based lookup-table devices —
Configuration Architecture Single-device configuration solution —
Architecture Block 1 Configuration controller —
Architecture Block 2 Flash memory —
Memory Technology Flash memory —
Supported Device Class SRAM-based LUT devices —
Configuration Mode [DATA_NEEDED: configuration mode] —
Memory Density [DATA_NEEDED: memory density] —
Configuration Data Interface [DATA_NEEDED: configuration data interface] —
Operating Voltage [DATA_NEEDED: operating voltage] —
Configuration Clock Frequency [DATA_NEEDED: configuration clock frequency] —
Package [DATA_NEEDED: package] —
Pin Count [DATA_NEEDED: pin count] —
Operating Temperature Range [DATA_NEEDED: operating temperature range] —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
REACH Status [DATA_NEEDED: REACH status] —
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 qualification] —
Memory Size — 1.6 Mb
Memory Organization — 1,695,680 x 1
Programmable Type — In System Programmable
Interface Type — Serial (for SRAM-based LUT FPGAs)
Programming Interface — IEEE 1532-compliant JTAG
Supply Voltage - VCCINT — 3.0 V to 3.6 V
Supply Voltage - VCCIO — 4.5 V to 5.5 V
Operating Temperature — -40 C to +85 C
Package / Case — 32-TQFP (7 mm x 7 mm)
Mounting Type — Surface Mount
Terminal Pitch — 0.8 mm
Supplier Device Package — 32-TQFP
Packaging — Tray
Technology — Flash + CMOS configuration logic
Configuration Clock — Dedicated DCLK output for FPGA
Lead-Free — [DATA_NEEDED: lead-free status]

Datasheets & Resources

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