EPC2C20 vs EPC2-TI32N 对比
详细并排对比 EPC2C20 出自 Altera 和 EPC2-TI32N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC2C20 | EPC2-TI32N |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | Memory ICs |
| 生命周期状态 | 有效 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $11.50 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| 封装 | [DATA_NEEDED: package] | — |
| 引脚数量 | [DATA_NEEDED: pin count] | — |
| 工作温度范围 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| 存储容量 | — | 1.6 Mb |
| Memory Organization | — | 1,695,680 x 1 |
| Programmable Type | — | In System Programmable |
| 接口类型 | — | Serial (for SRAM-based LUT FPGAs) |
| Programming Interface | — | IEEE 1532-compliant JTAG |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage - VCCIO | — | 4.5 V to 5.5 V |
| 工作温度 | — | -40 C to +85 C |
| 封装 / 外壳 | — | 32-TQFP (7 mm x 7 mm) |
| 安装类型 | — | Surface Mount |
| Terminal Pitch | — | 0.8 mm |
| Supplier Device Package | — | 32-TQFP |
| Packaging | — | Tray |
| Technology | — | Flash + CMOS configuration logic |
| Configuration Clock | — | Dedicated DCLK output for FPGA |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |