EPC2C20 vs EPC2-TI32N 比較
詳細な並列比較: EPC2C20 メーカー: Altera および EPC2-TI32N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC2C20 | EPC2-TI32N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | Memory ICs |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $11.50 |
| Manufacturer | Altera | — |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| パッケージ | [DATA_NEEDED: package] | — |
| ピン数 | [DATA_NEEDED: pin count] | — |
| 動作温度範囲 | [DATA_NEEDED: operating temperature range] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| メモリサイズ | — | 1.6 Mb |
| Memory Organization | — | 1,695,680 x 1 |
| Programmable Type | — | In System Programmable |
| インターフェースタイプ | — | Serial (for SRAM-based LUT FPGAs) |
| Programming Interface | — | IEEE 1532-compliant JTAG |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V |
| Supply Voltage - VCCIO | — | 4.5 V to 5.5 V |
| 動作温度 | — | -40 C to +85 C |
| パッケージ / ケース | — | 32-TQFP (7 mm x 7 mm) |
| 実装タイプ | — | Surface Mount |
| Terminal Pitch | — | 0.8 mm |
| Supplier Device Package | — | 32-TQFP |
| Packaging | — | Tray |
| Technology | — | Flash + CMOS configuration logic |
| Configuration Clock | — | Dedicated DCLK output for FPGA |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |