EPC2LI20 vs EPC2LC20 Comparison
Detailed side-by-side comparison of EPC2LI20 by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LI20 | EPC2LC20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.95 | $7.20 |
| Memory Size | 1.6 Mb (1,572,864 bits) | 1.6 Mbit |
| Memory Type | Flash (in-system programmable) | Non-volatile configuration PROM |
| Programmable Type | In System Programmable (ISP) | β |
| Function | Configuration PROM for SRAM-based FPGAs | β |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | β |
| Operating Temperature | -40 C to +85 C (Industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Package / Case | 20-PLCC (J-lead, 9x9 mm) | β |
| Mounting Type | Surface Mount (PLCC socket-compatible) | Surface Mount |
| Configuration Interface | Serial or Byte-wide (parallel) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Decompression | On-chip (supports compressed bitstreams) | β |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | β |
| Multi-Device Support | Yes (daisy-chain configuration) | β |
| User-Accessible Memory | Yes (unused flash available to user logic) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-Compliant (original Altera Pb-containing part) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Programming Interface | β | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | β | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | β | 5.0 V or 3.3 V |
| Supported FPGA Families | β | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | β | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Package | β | 20-pin PLCC (J-lead, 9x9 mm) |
| Lead-Free Version | β | EPC2LC20N available as lead-free equivalent |
| Programming Support | β | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | β | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |