EPC2LI20 vs EPC2LC20 比較
詳細並排比較 EPC2LI20 由 Altera 與 EPC2LC20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LI20 | EPC2LC20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | NRND | NRND |
| 單價 (USD) | — | $7.20 |
| 記憶體容量 | 1.6 Mb (1,572,864 bits) | 1.6 Mbit |
| 記憶體類型 | Flash (in-system programmable) | Non-volatile configuration PROM |
| Programmable Type | In System Programmable (ISP) | — |
| 功能 | Configuration PROM for SRAM-based FPGAs | — |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | — |
| 工作溫度 | -40 C to +85 C (Industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| 封裝 / 外殼 | 20-PLCC (J-lead, 9x9 mm) | — |
| 安裝類型 | Surface Mount (PLCC socket-compatible) | Surface Mount |
| Configuration Interface | Serial or Byte-wide (parallel) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Decompression | On-chip (supports compressed bitstreams) | — |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | — |
| Multi-Device Support | Yes (daisy-chain configuration) | — |
| User-Accessible Memory | Yes (unused flash available to user logic) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-Compliant (original Altera Pb-containing part) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| 封裝 | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |