EPC2LI20 vs EPC2LC20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LI20 sa pamamagitan ng Altera at EPC2LC20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2LI20 | EPC2LC20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | NRND | NRND |
| Presyo ng Yunit (USD) | — | $7.20 |
| Laki ng Memory | 1.6 Mb (1,572,864 bits) | 1.6 Mbit |
| Uri ng Memory | Flash (in-system programmable) | Non-volatile configuration PROM |
| Programmable Type | In System Programmable (ISP) | — |
| Fungsi | Configuration PROM for SRAM-based FPGAs | — |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | — |
| Temperature na Operasyon | -40 C to +85 C (Industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Packhaging / Kaso | 20-PLCC (J-lead, 9x9 mm) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket-compatible) | Surface Mount |
| Configuration Interface | Serial or Byte-wide (parallel) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Decompression | On-chip (supports compressed bitstreams) | — |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | — |
| Multi-Device Support | Yes (daisy-chain configuration) | — |
| User-Accessible Memory | Yes (unused flash available to user logic) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-Compliant (original Altera Pb-containing part) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Packhaging | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |