EPC2LI20 vs EPC2LC20-V Comparison
Detailed side-by-side comparison of EPC2LI20 by Altera and EPC2LC20-V by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LI20 | EPC2LC20-V |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.95 | $9.45 |
| Memory Size | 1.6 Mb (1,572,864 bits) | β |
| Memory Type | Flash (in-system programmable) | Configuration PROM (Flash-based, in-system programmable) |
| Programmable Type | In System Programmable (ISP) | β |
| Function | Configuration PROM for SRAM-based FPGAs | β |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | β |
| Operating Temperature | -40 C to +85 C (Industrial) | β |
| Package / Case | 20-PLCC (J-lead, 9x9 mm) | β |
| Mounting Type | Surface Mount (PLCC socket-compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Interface | Serial or Byte-wide (parallel) | Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) |
| Decompression | On-chip (supports compressed bitstreams) | β |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | β |
| Multi-Device Support | Yes (daisy-chain configuration) | β |
| User-Accessible Memory | Yes (unused flash available to user logic) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (per distributor listings) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Memory Density | β | 1.6 Mbit |
| Maximum Configuration Clock | β | 10 MHz |
| Supply Voltage VCC | β | 3.3 V |
| I/O Tolerance | β | 5 V tolerant on configuration pins |
| In-System Programming | β | Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) |
| Cascade Support | β | Yes, daisy-chainable for >1.6 Mbit designs |
| Operating Temperature Range (V suffix) | β | 0 Β°C to +70 Β°C (commercial) |
| Package Type | β | 20-pin PLCC (JEDEC MS-018) |
| Package Dimensions | β | 9 x 9 mm body, 1.27 mm pitch |
| Supported FPGA Families | β | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 |
| Lead-Free | β | Yes |