EPC2LI20 vs EPC2LC20-V 비교
다음의 상세 나란히 비교: EPC2LI20 제조: Altera 및 EPC2LC20-V 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPC2LI20 | EPC2LC20-V |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | Memory ICs | Memory ICs |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $5.95 | $9.45 |
| 메모리 크기 | 1.6 Mb (1,572,864 bits) | — |
| 메모리 유형 | Flash (in-system programmable) | Configuration PROM (Flash-based, in-system programmable) |
| Programmable Type | In System Programmable (ISP) | — |
| 기능 | Configuration PROM for SRAM-based FPGAs | — |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | — |
| 동작 온도 | -40 C to +85 C (Industrial) | — |
| 패키지 / 케이스 | 20-PLCC (J-lead, 9x9 mm) | — |
| 실장 유형 | Surface Mount (PLCC socket-compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Interface | Serial or Byte-wide (parallel) | Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) |
| Decompression | On-chip (supports compressed bitstreams) | — |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | — |
| Multi-Device Support | Yes (daisy-chain configuration) | — |
| User-Accessible Memory | Yes (unused flash available to user logic) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | Compliant (per distributor listings) |
| MSL 레벨 | [DATA_NEEDED: MSL level] | — |
| Memory Density | — | 1.6 Mbit |
| Maximum Configuration Clock | — | 10 MHz |
| Supply Voltage VCC | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant on configuration pins |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) |
| Cascade Support | — | Yes, daisy-chainable for >1.6 Mbit designs |
| Operating Temperature Range (V suffix) | — | 0 °C to +70 °C (commercial) |
| Package Type | — | 20-pin PLCC (JEDEC MS-018) |
| Package Dimensions | — | 9 x 9 mm body, 1.27 mm pitch |
| Supported FPGA Families | — | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 |
| Lead-Free | — | Yes |