EPF10K200SBC600-2 vs EPF10K100EBC356-2 Comparison
Detailed side-by-side comparison of EPF10K200SBC600-2 by Altera and EPF10K100EBC356-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPF10K100EBC356-2 - 100K Gates FLEX 10KE FPGA 274 I/O BGA-356 | Intel
EPF10K100EBC356-2 ObsoleteSpecification Comparison
| Parameter | EPF10K200SBC600-2 | EPF10K100EBC356-2 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $85.00 | $59.95 |
| Manufacturer | Altera (now Intel) | β |
| Series | FLEX-10KS | FLEX-10KE |
| Logic Elements / Cells | 9,984 | β |
| Logic Array Blocks (LABs) | 1,248 | β |
| Typical Gates | 200,000 | 100,000 |
| User I/Os | 470 | β |
| Propagation Delay | 0.4 ns | β |
| Voltage - Supply (VCCINT) | 2.375 V to 2.625 V | β |
| Operating Temperature | 0 C to 70 C | 0 C to 70 C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Package / Case | 600-BGA (45 x 45 mm, 1.27 mm pitch) | β |
| Supplier Device Package | 600-BGA | β |
| Logic Family | CMOS (SRAM-based) | β |
| Process Technology | 0.22 micrometer | CMOS, SRAM-based |
| Embedded Array Blocks (EABs) | Yes (for distributed RAM/ROM) | 12 |
| PLLs | 4 | β |
| Configuration Interface | IEEE 1149.1 JTAG | β |
| MultiVolt I/O | Yes (1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) | β |
| Packaging | Bulk / Tray | β |
| RoHS Status | Non-compliant | [DATA_NEEDED: RoHS compliance] |
| Family | β | Embedded Programmable Logic Device (PLD) |
| Maximum System Gates | β | 158,000 |
| Logic Elements (LEs) | β | 4,992 |
| Number of LABs/CLBs | β | 624 |
| Total RAM Bits | β | 49,152 |
| User I/O Pins | β | 274 |
| Supply Voltage (Core) | β | 2.375 V to 2.625 V (2.5 V nominal) |
| Propagation Delay (tPD) | β | 0.5 ns |
| Internal Operating Frequency | β | up to 250 MHz |
| Package Type | β | 356-LBGA (35 x 35 mm, 1.27 mm pitch) |
| Configuration Method | β | SRAM, JTAG (IEEE 1149.1) |
| Speed Grade | β | -2 |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |