EPF10K250EFC672-3 vs EPF10K250EFI672-3 Comparison
Detailed side-by-side comparison of EPF10K250EFC672-3 by Intel and EPF10K250EFI672-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPF10K250EFC672-3 | EPF10K250EFI672-3 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $99.50 | $125.00 |
| Product Type | FPGA (Field Programmable Gate Array) | β |
| Family | FLEX 10KE | FLEX 10KE |
| Maximum Typical Gates | 250,000 | β |
| Logic Elements (LEs) | 12,160 | β |
| Embedded Memory (EAB) | 655,360 bits (80 EABs x 2,048 bits each) | β |
| Logic Array Blocks (LABs) | 392 (8 LEs per LAB) | β |
| User I/O Pins | 470 | 470 |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | MultiVolt: 1.5 V / 1.8 V / 2.5 V / 3.3 V | 2.5 V / 3.3 V (multiVolt I/O) |
| Speed Grade | -3 (fastest) | β |
| Temperature Grade | Commercial (0C to +70C) | β |
| Package | 672-ball FineLine BGA (FC) | 672-ball FineLine BGA, 1.27 mm pitch |
| Ball Pitch | 1.0 mm | β |
| Configuration Mode | JTAG (IEEE 1149.1) ISP / serial / parallel, external EPCx PROM | β |
| Process Technology | 0.25 um CMOS, 5-layer metal | CMOS, SRAM-based configuration |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS status - 672-FBGA part is non-RoHS per Fly-Wing listing] | Unknown (legacy Altera non-RoHS device) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Typical Gates | β | 250,000 |
| Logic Elements | β | [DATA_NEEDED: exact LE count] |
| Embedded Array Blocks (EABs) | β | 12 |
| EAB Dual-Port Width | β | Up to 16-bit |
| Maximum EAB Memory | β | [DATA_NEEDED: bits per EAB] |
| Propagation Delay (tpd) | β | 0.4 ns (typical, -3 speed grade) |
| Configuration Interface | β | JTAG / ByteBlaster (EPC2/EPC8 PROM) |
| Operating Temperature | β | 0 Β°C to 70 Β°C (commercial) |
| Design Entry | β | EDIF 2 0 0 / 3 0 0, LPM, VHDL, Verilog |