EPM2210F256I5 vs EPM2210F256C5 Comparison
Detailed side-by-side comparison of EPM2210F256I5 by Altera and EPM2210F256C5 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM2210F256C5 - MAX II CPLD 1700 Macrocells 201MHz FBGA-256 | Altera / Intel
EPM2210F256C5 NrndSpecification Comparison
| Parameter | EPM2210F256I5 | EPM2210F256C5 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $20.80 | $14.95 |
| Family | MAX II | β |
| Series | MAX II CPLD | EPM2210 |
| Number of Macrocells | 1700 | β |
| Number of Logic Elements | 2210 | β |
| Maximum Internal Frequency | 201.1 MHz | 201.1 MHz |
| Maximum Propagation Delay (tpd) | 7.0 ns | β |
| Supply Voltage - Internal | 2.5 V, 3.3 V | β |
| Operating Temperature (TJ) | -40 C to +100 C | β |
| Package / Case | 256-FBGA (17x17) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programmable I/O Pins | [DATA_NEEDED: number of user I/O pins] | β |
| User Flash Memory | 8 Kbit | β |
| Number of Logic Array Blocks | 16 | β |
| I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| JTAG Compliant | Yes (IEEE 1149.1) | β |
| In-System Programmable | Yes (via ByteBlaster/USB-Blaster) | β |
| RoHS Status | Non-compliant (contains lead, per IC Components datasheet) | Compliant |
| Delivery Type | Tray | β |
| Device Family | β | MAX II |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells (Logic Elements) | β | 1700 |
| Propagation Delay | β | 5 ns (C5 speed grade) |
| User I/Os | β | 272 |
| Supply Voltage | β | 2.5 V / 3.3 V (MultiVolt I/O) |
| Process Technology | β | 0.18 Β΅m flash-based |
| Package | β | 256-ball FineLine BGA (FBGA-256) |
| Package Code | β | BGA, 17 x 17 mm, 1.0 mm pitch |
| Operating Temperature | β | 0C to +85C (commercial, C5 suffix) |
| Programming Interface | β | JTAG (IEEE 1149.1), in-system programmable |
| Configuration Memory | β | On-chip flash (instant-on, non-volatile) |
| On-chip User Flash Memory | β | 8 Kbits |
| MSL Level | β | 3 (per JEDEC J-STD-020) |