EPM3032ATC44-10NAA vs EPM3032ALC44-10N Comparison

Detailed side-by-side comparison of EPM3032ATC44-10NAA by Altera and EPM3032ALC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3032ATC44-10NAA EPM3032ALC44-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device —
Number of Macrocells 32 —
Number of Logic Array Blocks (LABs) 2 —
Usable Gates 600 —
Number of User I/O Pins 34 —
Propagation Delay (tpd) 10 ns —
Maximum Internal Frequency [DATA_NEEDED: fmax spec] —
Core Supply Voltage 3.3 V —
I/O Logic Levels Supported 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Programming Technology CMOS EEPROM (non-volatile) —
In-System Programming IEEE Std. 1149.1 JTAG + IEEE Std. 1532 —
Hot-Socketing Support Yes —
Package 44-pin TQFP 44-pin PLCC (J-Lead, surface mount)
Operating Temperature Range [DATA_NEEDED: operating temperature] —
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: compliant or non-compliant]
Lead-Free [DATA_NEEDED: lead-free status] —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 600 gates
Macrocells — 32
Logic Array Blocks (LABs) — 2
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Internal fMAX — 103.1 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Technology — CMOS EEPROM-based
In-System Programmability — Yes, via IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Yes, IEEE 1149.1 compliant
Operating Temperature — [DATA_NEEDED: industrial/commercial range]

Datasheets & Resources

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