EPM3032ATC44-10NAA vs EPM3032ALC44-10N 比較

詳細並排比較 EPM3032ATC44-10NAA 由 Altera 與 EPM3032ALC44-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3032ATC44-10NAA EPM3032ALC44-10N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device —
Number of Macrocells 32 —
Number of Logic Array Blocks (LABs) 2 —
Usable Gates 600 —
Number of User I/O Pins 34 —
Propagation Delay (tpd) 10 ns —
Maximum Internal Frequency [DATA_NEEDED: fmax spec] —
Core Supply Voltage 3.3 V —
I/O Logic Levels Supported 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Programming Technology CMOS EEPROM (non-volatile) —
In-System Programming IEEE Std. 1149.1 JTAG + IEEE Std. 1532 —
Hot-Socketing Support Yes —
封裝 44-pin TQFP 44-pin PLCC (J-Lead, surface mount)
工作溫度範圍 [DATA_NEEDED: operating temperature] —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: compliant or non-compliant]
Lead-Free [DATA_NEEDED: lead-free status] —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 600 gates
Macrocells — 32
Logic Array Blocks (LABs) — 2
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Internal fMAX — 103.1 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Technology — CMOS EEPROM-based
In-System Programmability — Yes, via IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Yes, IEEE 1149.1 compliant
工作溫度 — [DATA_NEEDED: industrial/commercial range]

資料表與資源

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