EPM3032ATC44-10NAA vs EPM3032ALC44-10N Vergleich
Detaillierter Direktvergleich von EPM3032ATC44-10NAA von Altera und EPM3032ALC44-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3032ATC44-10NAA - 32-Macrocell MAX 3000A CPLD, 44-TQFP | Altera
EPM3032ATC44-10NAA Obsolete
Spezifikationsvergleich
| Parameter | EPM3032ATC44-10NAA | EPM3032ALC44-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $0,94 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Number of Macrocells | 32 | — |
| Number of Logic Array Blocks (LABs) | 2 | — |
| Usable Gates | 600 | — |
| Number of User I/O Pins | 34 | — |
| Propagation Delay (tpd) | 10 ns | — |
| Maximum Internal Frequency | [DATA_NEEDED: fmax spec] | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Logic Levels Supported | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1149.1 JTAG + IEEE Std. 1532 | — |
| Hot-Socketing Support | Yes | — |
| Gehäuse | 44-pin TQFP | 44-pin PLCC (J-Lead, surface mount) |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature] | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: compliant or non-compliant] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 600 gates |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 2 |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal fMAX | — | 103.1 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| Technology | — | CMOS EEPROM-based |
| In-System Programmability | — | Yes, via IEEE 1149.1 JTAG |
| ISP Standard Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes, IEEE 1149.1 compliant |
| Betriebstemperatur | — | [DATA_NEEDED: industrial/commercial range] |