EPM3064ALC44-10N vs EPM3064ATC44-10 Comparison

Detailed side-by-side comparison of EPM3064ALC44-10N by Altera and EPM3064ATC44-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ALC44-10N EPM3064ATC44-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Product Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 —
Logic Array Blocks (LABs) 4 —
User I/O Pins 34 —
Usable Gates 1,250 1,250
Propagation Delay (tPD) 10 ns 10 ns
Maximum Counter Frequency 227.3 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V 3.0 V to 3.6 V (3.3 V typical)
I/O Bank Voltage (VCCIO) 3.0 V to 3.6 V (MultiVolt) MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V
Configuration Memory CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) —
Package 44-pin PLCC (LC44) TQFP-44, 10 x 10 mm, 0.8 mm pitch
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Operating Temperature [DATA_NEEDED: commercial / industrial grade] —
RoHS Status Compliant Non-compliant (legacy Altera, Pb-bearing)
Open-Drain Output Option Yes (per I/O pin) —
Output Slew-Rate Control Programmable —
Family — MAX 3000A
Logic Elements / Macrocells — 64 macrocells
Number of Logic Blocks / LABs — 4 LABs
Maximum Internal Frequency — 227.3 MHz (counter speed)
Programmable I/Os — 34
Technology — CMOS EEPROM, 5 V tolerant I/O
In-System Programming — IEEE Std. 1532 (JTAG)
Boundary-Scan Support — IEEE 1149.1 (JTAG)
Operating Temperature Range — 0C to +70C (commercial)

Datasheets & Resources

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