EPM3064ALC44-10N vs EPM3064ATC44-10 对比

详细并排对比 EPM3064ALC44-10N 出自 Altera 和 EPM3064ATC44-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ALC44-10N EPM3064ATC44-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $4.25 $4.35
Product Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 —
Logic Array Blocks (LABs) 4 —
User I/O Pins 34 —
Usable Gates 1,250 1,250
Propagation Delay (tPD) 10 ns 10 ns
Maximum Counter Frequency 227.3 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V 3.0 V to 3.6 V (3.3 V typical)
I/O Bank Voltage (VCCIO) 3.0 V to 3.6 V (MultiVolt) MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V
Configuration Memory CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) —
封装 44-pin PLCC (LC44) TQFP-44, 10 x 10 mm, 0.8 mm pitch
安装类型 Surface Mount (PLCC socket compatible) Surface Mount
工作温度 [DATA_NEEDED: commercial / industrial grade] —
RoHS 状态 Compliant Non-compliant (legacy Altera, Pb-bearing)
Open-Drain Output Option Yes (per I/O pin) —
Output Slew-Rate Control Programmable —
Family — MAX 3000A
Logic Elements / Macrocells — 64 macrocells
Number of Logic Blocks / LABs — 4 LABs
Maximum Internal Frequency — 227.3 MHz (counter speed)
Programmable I/Os — 34
Technology — CMOS EEPROM, 5 V tolerant I/O
In-System Programming — IEEE Std. 1532 (JTAG)
Boundary-Scan Support — IEEE 1149.1 (JTAG)
工作温度范围 — 0C to +70C (commercial)

数据手册与资源

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