EPM3064ATC-100-10N vs EPM3064AT100-10N Comparison
Detailed side-by-side comparison of EPM3064ATC-100-10N by Altera and EPM3064AT100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC-100-10N - 64-Macrocell MAX 3000A CPLD, 10ns | Altera
EPM3064ATC-100-10N β ActiveSpecification Comparison
| Parameter | EPM3064ATC-100-10N | EPM3064AT100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $2.20 | $5.45 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | β |
| Logic Array Blocks (LABs) | 2 | 4 |
| User I/O Pins | 66 | 66 |
| Usable Gates (min) | 600 | β |
| Usable Gates (typical) | 1,250 | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Counter Frequency (fCNT) | 227.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| In-System Programmability | Yes (IEEE 1532 / JTAG 1149.1) | β |
| Programming Interface | 4-pin JTAG (TCK/TMS/TDI/TDO) | JTAG (IEEE Std. 1149.1) with pin-locking |
| Package | TQFP-100 | TQFP-100 (T100), 14 mm x 14 mm |
| Mounting Type | Surface Mount | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | β | 64 |
| Usable Gates | β | 1,250 |
| Speed Grade | β | -10 (10 ns pin-to-pin delay) |
| I/O Bank Voltage | β | 3.3 V |
| 5 V Tolerant Inputs | β | Yes (via clamping diodes) |
| Configuration Memory | β | EEPROM (non-volatile) |
| ISP Compliance | β | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | β | IEEE Std. 1149.1 compliant |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Lead-Free | β | [DATA_NEEDED: lead-free finish] |